Overview
China’s domestic AI compute chips have debuted across multiple fronts. At WAIC 2026, Baidu’s Kunlunxin unveiled the physical fourth-generation AI chip M100. Continuing its in-house XPU architecture and optimized for large-model inference, M100 emphasizes versatility, efficiency and deployment cost, built on a fully domestic supply chain and aimed at large-scale inference; Baidu’s U.S.-listed shares rose over 3% in premarket. The lineup splits: M100 targets inference, while M300 (planned for 2027) addresses ultra-large multimodal training and inference.
Automotive and data-center scenes broke through in parallel. On October 19 at the RISC-V China Summit in Shenzhen, Alibaba’s Damo Academy released the Xuantie E908A automotive-enhanced processor—the first RISC-V CPU IP to simultaneously meet ASIL-B and ASIL-D, with a single-point fault metric (SPFM) above 90% for the first time in the industry; it also unveiled roadmaps for autonomous driving and embodied intelligence, with next-gen C950A targeting 5x current automotive performance. The same day, ZTE Microelectronics’ Lirui Micro showed “Everest 200,” the industry’s first RISC-V CPU chip for intelligent computing centers, focusing on Agent clusters and inference super-node hosts, with native RISC-V AI instruction acceleration and deep optimization for KV Cache and long-context inference.
The cluster of launches reflects a clear trend: amid surging inference demand and persistent external compute controls, domestic chips are breaking through via two parallel paths—“in-house architecture + fully local supply chain” and “open RISC-V ecosystem”—shifting competition from peak FLOPS to supply-chain security and scenario fit.
Background & Interpretation
1. Technical Background and Evolution
The dimension of AI-chip competition is being rebuilt. Peak TFLOPS once ruled; in the inference era, task completion per cost, energy efficiency and deployment flexibility matter more. Kunlunxin’s fully local supply chain directly answers external controls and supply uncertainty; Xuantie E908A and Everest 200 bet on RISC-V to escape x86/ARM licensing constraints and build autonomous foundations in automotive and compute-center scenes.
2. Core Drivers and Underlying Mechanisms
The two paths differ mechanistically. Kunlunxin leverages inference loads honed by Baidu’s search, ads and ERNIE traffic to forge a cost-efficient XPU; the RISC-V camp uses modularity to go deep on automotive safety (ASIL) and compute-center long-context inference (KV Cache optimization). Both point to “software-hardware co-design”—chips must bind tightly with application stacks, compilers and frameworks to realize value.
3. Market Structure and Industrial Chain Impact
The collective debut reshapes AI-infrastructure supply. For cloud and enterprise customers, more domestic options lift procurement leverage and resilience; for international vendors like Nvidia, China substitution pressure grows; for OEMs and solution providers, adaptation layers must be rebuilt for diverse architectures. Yet process nodes, ecosystem maturity and software toolchains remain near-term gaps; yield and scale effects decide final cost.
Implications & Outlook
Near-to-medium term, inference chips and RISC-V will be the main breakthrough theaters, with automotive and compute centers leading volume. Watch domestic supply-chain yield and capacity, RISC-V software maturity (compilers/frameworks), and the durability of large-model inference demand. With ecosystems filled, domestic chips could scale substitution on the inference side.
Takeaways for Industry Participants
Chip firms should focus on real-scenario loads and software-hardware co-design rather than raw FLOPS. Cloud and enterprise customers can pilot domestic chips incrementally and build multi-vendor strategies. Developers should track RISC-V and domestic toolchain adaptation. Investors should back teams with clear scenarios and supply-chain control.
This column compiles industry information and shares technical perspectives; it does not constitute investment advice.