Overview
From October 18 to 20, the 6th RISC-V China Summit was held in Shenzhen with over 450 exhibitors, sending a clear signal: China’s chip industry is seizing the AI-compute opportunity through an open-source architecture. The flagship breakthrough was the server-grade V100 chip jointly released by SpacemiT and the Chinese Academy of Sciences’ XiangShan team—the industry’s first general-purpose compute chip fully compliant with the complete server specification.
V100 took about three years, with key IP self-developed, solving server-scene binary-compatibility so it can deploy directly into existing data centers without per-chip OS customization. SpacemiT simultaneously launched general-compute, AI-compute and mass-storage server systems, marking RISC-V’s formal move into scalable data-center markets.
Alibaba’s DAMO Academy also announced T-Head shipments surpassing 6 billion units and an automotive-grade processor; Chrex showcased high-performance cores and edge-AI cluster solutions supporting LLM inference and robot debugging.
Background & Interpretation
1. Technical Background and Evolution
RISC-V is a streamlined instruction set that, being fully open and freely extensible, breaks the closed-license barriers of x86 and Arm, opening a new track for domestic mastery of open architectures. Early RISC-V lived in low-power MCUs and IoT; after the AI-compute surge, industry began exploring open architectures for cloud tasks. A noted shift at this summit: focus moved rapidly from embedded controllers to mid/high-performance and even server-grade chips, with nearly a third of exhibitors centering on AI fusion.
2. Core Drivers and Underlying Mechanism
AI-compute applications are the new direction; massive new compute pushes open architectures to absorb cloud workloads. V100’s value is “binary compatibility”—direct data-center deployment lowering migration cost and gaining discourse power in the global open-source community. The Beijing Open-Source Chip Research Institute notes RISC-V has become “an instruction-set ecosystem born for AI.” China’s complete supply chain and rich embodied-AI/robotics scenes naturally suit new-architecture incubation.
3. Market Structure and Industry Chain Impact
The RISC-V ecosystem is leaping from “IoT MCU” to “server + AI,” benefiting local IP, EDA, foundries and OEMs. T-Head’s 6 billion shipments prove open architecture’s scale at the edge; V100 opens the data-center increment. The challenge is software ecosystem (OS, compilers, AI-framework adaptation) still maturing; competing with mainstream architectures depends on developers and flagship deployments.
Implications & Outlook
Near term, the summit boosts confidence in domestic open-source chips and accelerates server- and auto-grade products. Medium term, RISC-V penetrates AI inference, edge computing and robot controllers, forming a “general + dedicated” complement to x86/Arm. Long term, open ISAs may become a key base for compute autonomy under geopolitical constraints, but ecosystem maturity sets the ceiling.
Takeaways for Industry Participants
Chip and OEM firms: use open architectures to cut license dependence, focus on server-spec compatibility and AI-scene systems. AI and robotics firms: exploit RISC-V’s open extensibility for custom cores, binding local supply chains. Developers: join the community, contribute binary-compatibility and AI-framework adapters. Investors: watch self-developed IP, automotive-grade and edge-AI clusters; beware immature-ecosystem risk.
This column compiles industry information and shares technical perspectives; it does not constitute investment advice.