Overview
China’s domestic AI compute chips posted a cluster of advances. On October 30, GPU maker Moore Threads reported Q3 revenue of RMB 1.552 billion, up 1773.92% YoY, with RMB 20.07 million in non-GAAP net profit turning positive; nine-month revenue reached RMB 3.29 billion, marking passage of the scale-driven break-even point. The same day, embodied-AI chip firm Beijing Huixi Technology filed IPO tutoring with the securities regulator, with CITIC Securities as sponsor—signaling capital concentrating upstream along the “compute–body” chain.
Separately, Huawei’s six-year “Tao (τ) Law” technology drew attention: abandoning traditional geometric scaling for a “time-scaling” approach, its logic-folding Kirin chip will mass-produce this autumn, redefining the chip evaluation system; the Mate 90 series fully adopts it with up to 31% performance gain. Reports also say TSMC may raise CoWoS advanced-packaging prices by up to 20% as AI demand tightens packaging capacity.
The signals show AI compute supply expanding and upgrading in parallel, with domestic substitution interwoven with international competition.
Background & Interpretation
1. Technical Background and Evolution
Exploding training and inference demand for large models shifted compute from “adequate” to “dedicated, efficient, autonomous.” Heavy reliance on advanced-node GPUs, plus geopolitical and supply constraints, pushed domestic chips toward differentiated paths in architecture, packaging and system integration. Huawei’s logic-folding, Moore Threads’ GPU scaling and Huixi’s embodied chips map to three needs: general compute, graphics/AI acceleration and robot edge inference.
2. Core Drivers and Underlying Mechanism
Moore Threads’ profit turn reflects released domestic AI/graphics demand and GPU penetration in Xinchuang and inference. Huixi’s IPO bid reflects rigid demand for embodied-specific chips (high real-time, low power, strong perception) being capitalized. Huawei’s Tao Law bypasses some process bottlenecks via time-dimensional architecture innovation. CoWoS hikes reveal advanced packaging as the new bottleneck of compute expansion.
3. Market Structure and Industry Impact
Compute-chip competition is moving from “single-chip performance” to “system integration”—inter-chip interconnect, system power delivery and optical interconnect are now focal, with chiplets and heterogeneous integration as high-end directions. Domestic breakthroughs across GPU, ASIC and edge-AI chips drive coordination in packaging, EDA and memory (HBM), yet advanced process, equipment and ecosystem remain long-term gaps.
Implications & Outlook
Near to medium term, domestic compute chips enter a “volume validation + capital support” window. Key variables: Moore Threads’ sustained profit quality, Huixi’s IPO progress and use of proceeds, the pace of advanced-packaging relief, and Huawei’s Tao-chip penetration in terminals and industry. If domestic chips build synergy on cost-performance and autonomy, they could reshape global compute supply.
Takeaways for Industry Participants
Cloud and AI firms can watch domestic GPU substitution windows in inference and Xinchuang to diversify supply risk. Terminal and robotics makers should pre-assess embodied-chip supply and software-hardware co-design. Investors should evaluate along the “chip–packaging–memory–system” chain while guarding against process limits, valuation bubbles and capacity mismatch.
This column compiles industry information and shares technical perspectives; it does not constitute investment advice.